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| RDC(R) R1620 RISC DSP Communication FAST ETHERNET RISC PROCESSOR FAST ETHERNET RISC PROCESSOR R1620 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 5 REV 1.0 Sep. 20 2006 RDC(R) 1. Features l l l R1620 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Five-stage pipeline RISC architecture Bus interface - Multiplexed address and Data bus - Supports non-multiplexed address bus A[19:0] - 8-bit or 16-bit external bus dynamic access - 1M-byte memory address space - 64K-byte I/O space - Supports an independent bus for slower I/O device l l Three independent 16-bit timers and one independent programmable watchdog timer The Interrupt controller with six maskable external interrupts and two non-maskable external interrupt l l l l l l l l Two independent DMA channels Programmable chip-select logic for Memory or I/O bus cycle decoder Programmable wait-state generator With 8-bit or 16-bit Boot ROM bus size 2-Port Fast Ethernet MAC with MII interface With 25MHz input frequency and up to 4x25MHz maximum internal frequency. Compatible with 3.3V I/O. Package Types include 160-pin PQFP and 160-pin LQFP. l l l l l Software is compatible with the 80C186 microprocessor Supports two 16550 UART serial channel with 16 bytes FIFO. Supports CPU ID Supports 32 PIO pins SDRAM control Interface Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 5 REV 1.0 Sep. 20 2006 RDC(R) R1620 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 2. Block Diagram INT2/INTA0_n INT1/SELECT_n CLKOUTA INT3/INTA1_n/IRQ INT[6:5] INT0 NMI TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST_n MAC1 MII 1 LCS_n/ONCE0_n UCS_n/ONCE1_n PCS5_n PCS6_n Chip Select Unit Instruction Queue (64bits) Instruction Decoder Control Signal MAC0 Micro ROM PIO Unit EA / LA Address 16550 UART Serial Port0 MII 0 ARDY SRDY DT/R_n DEN_n HOLD HLDA SD_CLK CKE CS_n WE_n CAS_n RAS_n BA Refresh Control Unit Register File General, Segment, Eflag Register SDRAM/Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit 16550 UART Serial Port1 DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n DCD1_n SIN1 DSR1_n CTS1_n RI1_n RTS1_n SOUT1 DTR1_n A[19:0] AD[15:0] RD_n WHB_n WLB_n/ADEN_n ALE WR_n/BWSEL Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 5 REV 1.0 Sep. 20 2006 RDC(R) 3. PQFP 160 pins R1620 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Package Information 31.2 0.25mm 28.0 0.1mm 120 81 121 80 RDC R1620 XXXX-B-QF XX-XXXXX 31.2 0.25mm 28 0.1mm 160 PIN 1 IDENTIFIER 1 0.65mm BSC 0.30 0.05mm 15 REF A2 = 3.22 0.07mm A = 4.07mm (max.) A2 40 41 0.18 0.05mm A1 = 0.25mm (min.) 10 REF Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 5 REV 1.0 Sep. 20 2006 RDC(R) LQFP 160 pins R1620 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 26mm BSC 24mm BSC 120 81 121 80 RDC R1620 XXXX-B-LQ XX-XXXXX 26mm BSC 24mm BSC 160 PIN 1 IDENTIFIER 1 0.5mm BSC 0.22 0.05mm 40 12 1 REF 41 A2 = 1.4 0.05mm A = 1.6mm (max.) A2 A1 = 0.1 0.05mm 12 1 REF 0.145 0.055mm Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 5 REV 1.0 Sep. 20 2006 |
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